Hard

Design an LLM Inference Performance Optimization Program System Design Interview

Design the measurement, kernel, rollout, and correctness system that closes the gap between theoretical and achieved inference throughput.

1. Problem Statement

Your inference fleet is 35% below expected throughput and p99 latency regressed after a runtime update. Design the system and process to diagnose and safely improve it.

2. Architecture Discussion Map

Use this as one discussion aid, not a single correct answer. Your design should follow from the requirements, scale, and trade-offs you establish.

Rendering architecture diagram...
Mermaid Source (For AI Bots)
graph LR
    A["Design an LLM Inference Performance Optimization Program"]
    A --> F1["Cross-layer latency and throughput attribution"]
    A --> F2["Roofline analysis and representative benchmarks"]
    A --> F3["Kernel fusion, memory bandwidth, and variable sequence lengths"]
    A --> F4["Quantization and numerical correctness"]
    A --> F5["Canary rollout, regression detection, and rollback"]

3. Key Focus Areas

  • 1
    Cross-layer latency and throughput attribution
  • 2
    Roofline analysis and representative benchmarks
  • 3
    Kernel fusion, memory bandwidth, and variable sequence lengths
  • 4
    Quantization and numerical correctness
  • 5
    Canary rollout, regression detection, and rollback

4. What Strong Candidates Should Demonstrate

  • Trace latency across routing, batching, runtime, kernels, memory, and hardware.
  • Use roofline and FLOPs funnels rather than isolated microbenchmarks.
  • Treat output correctness as a release gate for optimization.

Evaluation Guide

This is an evaluation framework, not a single model answer. Strong designs may make different choices when their assumptions and trade-offs are explicit.

Measurement and attribution

30%

Senior signals

  • Builds end-to-end traces and a FLOPs or latency funnel from queue to kernel.
  • Uses production-representative prompt lengths, batch shapes, and hardware.

Optimization strategy

25%

Senior signals

  • Distinguishes compute-bound and memory-bound phases.
  • Discusses fusion, layout, occupancy, communication overlap, batching, and cache behavior.

Correctness

25%

Senior signals

  • Defines golden outputs, tolerance, task evals, hardware-specific comparison, and quantization gates.
  • Rejects improvements that silently damage model quality.

Rollout and economics

20%

Senior signals

  • Canaries by hardware/workload, monitors p50/p99 and cost per token, and supports fast rollback.
  • Prioritizes changes by fleet-level impact rather than benchmark vanity.

Trade-offs to articulate

  • Kernel specialization versus maintainability.
  • Precision reduction versus quality.
  • Batch size versus latency.

Practice follow-up questions

  1. 1.A kernel is 2x faster in isolation but fleet throughput does not move. Why?
  2. 2.FP8 improves speed but one task family regresses. What is your release decision?

Want interactive feedback?

Practice drawing this system component-by-component on a live whiteboard while the interviewer probes at your target level.

Start Interview

Core Concepts

CUDARoofline AnalysisKernel FusionQuantizationPerformance Evals